基于VHDL的四路抢答器设计

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity carrie is
 port
 (
    CLK:std_logic;   --扫描脉冲
  host  : in std_logic;  --主持人信号
  answer  : in std_logic_vector(3 downto 0);  --抢答信号
  light  : out std_logic_vector(3 downto 0)   --指示灯
 );
end entity;
architecture rtl of carrie is

signal lock:std_logic;   --定义一个‘锁’信号使得一人抢答后其他人不能再抢答
begin
 process (host,answer,CLK)
 begin
  if(host='0')then   -- 主持人清零
   light<="0000";   --清零
    lock<='0';
  elsif (HOST='1')then    --主持人置‘1’，开始抢答
    IF(LOCK='0') THEN    --控制 信号，完成只能有一路选通
    IF(CLK'EVENT AND CLK='1') THEN        --脉冲扫描
   case answer is
   when "1000"=>light<="1000";lock<='1';   --lock 信号使得一人抢答后其他人不能再抢答上
   when "0100"=>light<="0100";lock<='1';
   when "0010"=>light<="0010";lock<='1';
   when "0001"=>light<="0001";lock<='1';
   when others=>light<="0000";
   end case;
  end if;
end if;
end if;
 end process;
end rtl;