问题描述

我是新手刚学verilog,自己写了段程序警告太多跪求大神指点

module a(nrst,clk,a,C1,C2,C3,C4,C5,C6,C7,C8,C9,C10,C11);input nrst,clk;input[3:0]a;output [3:0]C1,C2,C3,C4,C5,C6,C7,C8,C9,C10,C11;reg [3:0]C1,C2,C3,C4,C5,C6,C7,C8,C9,C10,C11;reg [3:0] CS,NS;parameter[3:0]IDLE=4'b0000,S1=4'b0001,S2=4'b0010,S3=4'b0011,S4=4'b0100,S5=4'b0101,S6=4'b0110,S7=4'b0111,S8=4'b1000,S9=4'b1001,S10=4'b1010;always@(posedge clk,negedge nrst)beginif(!nrst) CS<=IDLE;else CS<=NS;endalways@(CS,a)begincase(CS) S1:begin if(a&&4'b0001) NS=S1; end S2:begin if(a&&4'b0010) NS=S2; end S3:begin if(a&&4'b0011) NS=S3; end S4:begin if(a&&4'b0100) NS=S4; end S5:begin if(a&&4'b0101) NS=S5; end S6:begin if(a&&4'b0110) NS=S6; end S7:begin if(a&&4'b0111) NS=S7; end S8:begin if(a&&4'b1000) NS=S8; end S9:begin if(a&&4'b1001) NS=S9; end S10:begin if(a&&4'b1010) NS=S10; end default:begin NS=IDLE; end endcaseendalways@(posedge clk,negedge nrst)begin case(NS) S1:C1<=4'b0001; S2:C2<=4'b0010; S3:C3<=4'b0011; S4:C4<=4'b0100; S5:C5<=4'b0101; S6:C6<=4'b0110; S7:C7<=4'b0111; S8:C8<=4'b1000; S9:C9<=4'b1001; S10:C10<=4'b1010; default:C11<=4'b0000; endcase end endmodule