问题描述

verilog大神请进来看看 小弟跪谢

我用quartusii仿真出现的情况 用Cyclone III仿真出现的严重警告但是 但是用其他器件仿真就不会出现严重警告 请问一下怎么解决 还有为什么用Cyclone III仿真就会出现严重警告
Critical Warning: Synopsys Design Constraints File file not found: 'test.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.Critical Warning: The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.
Critical Warning: Found minimum pulse width or period violations. See Report Minimum Pulse Width for details.
Critical Warning: Timing requirements not met

解决方案

http://www.1point3acres.com/bbs/thread-38850-1-1.html