问题描述

verilog 红绿灯设计状态机代码不理解

module sheJiShuRu(
input clk reset Ta Tb clr
output reg [1:0] La Lb
output reg mclk
);

 reg [31:0] count; parameter CLK_COUNT = 249999999; //parameter CLK_COUNT = 24;//模拟用 always @ (posedge clk)  begin    if(clr)    //按下去（为1？）复位     begin      count <= 0;      mclk <= 0;     end   else if(count == CLK_COUNT)    //用到了前面定义的参数     begin      count <= 0;      mclk <= ~mclk;     end    else     count <= count+1;  end reg [1:0] state next_state; parameter S0 = 2'b00; parameter S1 = 2'b01; parameter S2 = 2'b10; parameter S3 = 2'b11; parameter green = 2'b00; parameter yellow = 2'b01; parameter red = 2'b10; always @ (posedge mclk)    if(reset)        state <= S0;    else        state <= next_state; always @(*)    case(state)        S0:             if(Ta) next_state = S0;            else next_state = S1;        S1: next_state = S2;        S2:             if(Tb) next_state = S2;            else next_state = S3;        S3: next_state = S0;    endcasealways @(*)  case(state)        S0:            begin                La = green;                Lb = red;            end        S1:            begin                La = yellow;                Lb = red;            end        S2:            begin                La = red;                Lb = green;            end        S3:            begin                La = red;                Lb = yellow;            end  endcase

endmodule

代码中最开始分频的部分有什么作用