问题描述

求大神帮我看一下代码哪里有问题，这是用verilog写的sdram的数据模块

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12:07:50 04/20/2016
// Design Name:
// Module Name: datagene
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module datagene(clk,rst_n,
sdram_wr_ack,sdram_rd_ack,
syswr_done,
sdram_wr_req,sdram_rd_req,
sys_data_in,sys_addr
);
input clk; //FPAG输入时钟信号150MHz
input rst_n; //FPGA输入复位信号

//wrFIFO输入控制接口

output[31:0] sys_data_in; //sdram数据写入缓存FIFO输入数据总线
output sdram_wr_req; //sdram数据写入缓存FIFO数据输入请求，高有效
output sdram_rd_req;
output[20:0] sys_addr; //sdram读写地址产生
output syswr_done; //所有数据写入sdram完成标志位

input sdram_rd_ack; //系统读SDRAM响应信号,作为sdram的输写有效信号,这里捕获它的下降沿作为读地址自增加标志位
input sdram_wr_ack;
reg sdr_rdackr1,sdr_rdackr2;

//------------------------------------------
//捕获sdram_rd_ack下降沿标志位
always @(posedge clk or negedge rst_n)

if(!rst_n) begin
sdr_rdackr1 <= 1'b0;
sdr_rdackr2 <= 1'b0;
end
else begin
sdr_rdackr1 <= sdram_rd_ack;
sdr_rdackr2 <= sdr_rdackr1;

end

wire neg_rdack = ~sdr_rdackr1 & sdr_rdackr2;

//------------------------------------------
//上电500us延时等待sdram就绪
reg[16:0] delay; //500us延时计数器

always @(posedge clk or negedge rst_n)
if(!rst_n) delay <= 17'd0;
else if(delay < 17'd74963) delay <= delay+1'b1;

wire delay_done = (delay == 17'd74963); //1ms延时结束

//------------------------------------------
//每511clk写入256个32bit数据到sdram，

(* KEEP = "TRUE" *) reg[8:0] cntwr; //写sdram定时计数器

always @(posedge clk or negedge rst_n)
if(!rst_n)
begin
cntwr[8:0] <= 9'd0;
end
else if(delay_done)
begin
cntwr[8:0] <= cntwr[8:0] + 1'b1;
end

//------------------------------------------
//读写sdram地址产生
reg[10:0] addr; //sdram地址寄存器
always @(posedge clk or negedge rst_n)
if(!rst_n) addr <= 11'b0;
else if(!wr_done)
begin
if(cntwr == 9'd511) addr <= addr+1'b1;//写地址产生
else if(addr==11'h7ff) addr<=11'b0;
end
else if(wr_done) //读地址产生 ////////////test
begin
if(neg_rdack) addr <= addr+1'b1;
else if(addr==11'h7ff) addr<=11'b0;
end
assign sys_addr = {2'b00,addr,8'b00000000};

reg wr_done; //所有数据写入sdram完成标志位

always @(posedge clk or negedge rst_n)
if(!rst_n) wr_done <= 1'b0;
else if(addr == 11'h7ff) wr_done<=~wr_done;
else wr_done<=wr_done;

assign syswr_done = wr_done;

//------------------------------------------
//写sdram请求信号产生，即sdram的写入有效信号
reg sdram_wr_reqr; //写入有效信号
reg[31:0] sys_data_inr; //写入数据

always @(posedge clk or negedge rst_n)
if(!rst_n)
begin
sdram_wr_reqr <= 1'b0;
end
else if(!wr_done)
begin //上电0.5ms延时完成
if(cntwr[8:0] <= 9'd6)
begin
sdram_wr_reqr <= 1'b1; //写请求信号产生
end
else if(cntwr[8:0] <= 9'd267)
begin
sdram_wr_reqr <= 1'b0; //请求信号撤销
end
else
begin
sdram_wr_reqr <= sdram_wr_reqr;
end
end

always @(posedge clk or negedge rst_n)
if(!rst_n) sys_data_inr <= 32'd0;
else if(sdram_wr_ack&& (!wr_done) && ((cntwr > 9'd7) && (cntwr <= 9'd263)))
begin

sys_data_inr <= sys_data_inr+1'b1; //写入数据递增,256个周期递增256,11~266clk
end
//读请求
reg sdram_rd_reqr;
always @(posedge clk or negedge rst_n)
if(!rst_n)
begin
sdram_rd_reqr <= 1'b0;
end
else if(wr_done)
begin //上电0.5ms延时完成
if(cntwr[8:0] <= 9'd6)
begin
sdram_rd_reqr <= 1'b1; //读请求信号产生
end
else if(cntwr[8:0] <= 9'd271)
begin
sdram_rd_reqr <= 1'b0; //请求信号撤销
end
else
begin
sdram_rd_reqr <= sdram_rd_reqr;
end
end
assign sdram_rd_req = sdram_rd_reqr;

assign sdram_wr_req = sdram_wr_reqr;
assign sys_data_in = sys_data_inr;

endmodule